<!DOCTYPE html>

<html>
<head>
<meta charset="UTF-8">
<link href="style.css" type="text/css" rel="stylesheet">
<title>MOVHPD—Move High Packed Double-Precision Floating-Point Value </title></head>
<body>
<h1>MOVHPD—Move High Packed Double-Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>66 0F 16 /r</p>
<p>MOVHPD xmm1, m64</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move double-precision floating-point value from m64 to high quadword of xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 16 /r</p>
<p>VMOVHPD xmm2, xmm1, m64</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Merge double-precision floating-point value from m64 and the low quadword of xmm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.W1 16 /r</p>
<p>VMOVHPD xmm2, xmm1, m64</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Merge double-precision floating-point value from m64 and the low quadword of xmm1.</td></tr>
<tr>
<td>
<p>66 0F 17 /r</p>
<p>MOVHPD m64, xmm1</p></td>
<td>MR</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move double-precision floating-point value from high quadword of xmm1 to m64.</td></tr>
<tr>
<td>
<p>VEX.128.66.0F.WIG 17 /r</p>
<p>VMOVHPD m64, xmm1</p></td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move double-precision floating-point value from high quadword of xmm1 to m64.</td></tr>
<tr>
<td>
<p>EVEX.128.66.0F.W1 17 /r</p>
<p>VMOVHPD m64, xmm1</p></td>
<td>T1S-MR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move double-precision floating-point value from high quadword of xmm1 to m64.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>T1S-MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>This instruction cannot be used for register to register or memory to memory moves.</p>
<p><strong>128-bit Legacy SSE load:</strong></p>
<p>Moves a double-precision floating-point value from the source 64-bit memory operand and stores it in the high 64-bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of the corresponding destination register are preserved.</p>
<p><strong>VEX.128 &amp; EVEX encoded load:</strong></p>
<p>Loads a double-precision floating-point value from the source 64-bit memory operand (the third operand) and stores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source operand (second operand) are copied to the low 64-bits of the destination. Bits (MAX_VL-1:128) of the corre-sponding destination register are zeroed.</p>
<p><strong>128-bit store:</strong></p>
<p>Stores a double-precision floating-point value from the high 64-bits of the XMM register source (second operand) to the 64-bit memory location (first operand).</p>
<p>Note: VMOVHPD (store) (VEX.128.66.0F 17 /r) is legal and has the same behavior as the existing 66 0F 17 store. For VMOVHPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.</p>
<p>If VMOVHPD is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L’L= 1 will cause an #UD exception.</p>
<p><strong>Operation</strong></p>
<p><strong>MOVHPD (128-bit Legacy SSE load)</strong></p>
<p>DEST[63:0] (Unmodified)</p>
<p>DEST[127:64] (cid:197) SRC[63:0]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>VMOVHPD (VEX.128 &amp; EVEX encoded load)</strong></p>
<p>DEST[63:0] (cid:197) SRC1[63:0]</p>
<p>DEST[127:64] (cid:197) SRC2[63:0]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VMOVHPD (store)</strong></p>
<p>DEST[63:0] (cid:197) SRC[127:64]</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>MOVHPD __m128d _mm_loadh_pd ( __m128d a, double *p)</p>
<p>MOVHPD void _mm_storeh_pd (double *p, __m128d a)</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 5; additionally</p>
<table>
<tr>
<td>#UD</td>
<td>
<p>If VEX.L = 1.</p>
<p>EVEX-encoded instruction, see Exceptions Type E9NF.</p></td></tr></table></body></html>